diff --git a/src/mainboard/piesia/Kconfig b/src/mainboard/piesia/Kconfig
new file mode 100644
index 0000000000..8f6428f666
--- /dev/null
+++ b/src/mainboard/piesia/Kconfig
@@ -0,0 +1,21 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if VENDOR_PIESIA
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/piesia/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/piesia/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "Piesia"
+
+config MAINBOARD_FAMILY
+	string
+	default MAINBOARD_PART_NUMBER
+
+endif # VENDOR_PIESIA
diff --git a/src/mainboard/piesia/Kconfig.name b/src/mainboard/piesia/Kconfig.name
new file mode 100644
index 0000000000..a2b1329ecf
--- /dev/null
+++ b/src/mainboard/piesia/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config VENDOR_PIESIA
+	bool "Piesia"
diff --git a/src/mainboard/piesia/nm19ne4l/Kconfig b/src/mainboard/piesia/nm19ne4l/Kconfig
new file mode 100644
index 0000000000..0d781d2230
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/Kconfig
@@ -0,0 +1,33 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_PIESIA_NM19NE4L
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select VGA_ROM_RUN
+	select SOC_INTEL_BAYTRAIL
+	select SUPERIO_ITE_IT8613E
+
+config CBFS_SIZE
+    default 0x500000
+
+config MAINBOARD_DIR
+	default "piesia/nm19ne4l"
+
+config MAINBOARD_PART_NUMBER
+	default "NM19NE4L"
+
+config MAINBOARD_SMBIOS_MANUFACTURER
+	string
+	default "Piesia"
+
+config SEABIOS_HARDWARE_IRQ
+	bool
+	default n
+
+endif # BOARD_PIESIA_NM19NE4L
diff --git a/src/mainboard/piesia/nm19ne4l/Kconfig.name b/src/mainboard/piesia/nm19ne4l/Kconfig.name
new file mode 100644
index 0000000000..6d0b902a6b
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_PIESIA_NM19NE4L
+	bool "NM19NE4L"
diff --git a/src/mainboard/piesia/nm19ne4l/Makefile.mk b/src/mainboard/piesia/nm19ne4l/Makefile.mk
new file mode 100644
index 0000000000..11a2a4a506
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/Makefile.mk
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += irqroute.c gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c
diff --git a/src/mainboard/piesia/nm19ne4l/acpi/ec.asl b/src/mainboard/piesia/nm19ne4l/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/piesia/nm19ne4l/acpi/mainboard.asl b/src/mainboard/piesia/nm19ne4l/acpi/mainboard.asl
new file mode 100644
index 0000000000..d679d2e2bb
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/acpi/mainboard.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * NOTE: this has to be here even when the board has no LPE audio, otherwise
+ * it breaks the SOC specific ACPI code
+ */
+Scope (\_SB.PCI0.LPEA)
+{
+	Name (GBUF, ResourceTemplate () {})
+}
diff --git a/src/mainboard/piesia/nm19ne4l/acpi/superio.asl b/src/mainboard/piesia/nm19ne4l/acpi/superio.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/piesia/nm19ne4l/acpi_tables.c b/src/mainboard/piesia/nm19ne4l/acpi_tables.c
new file mode 100644
index 0000000000..d53e97c6d9
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/acpi_tables.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+	/* TPM not present */
+	gnvs->tpmp = 0;
+
+	/* Disable DPTF */
+	gnvs->dpte = 0;
+}
+
+void mainboard_fill_fadt(acpi_fadt_t *fadt)
+{
+	fadt->preferred_pm_profile = PM_DESKTOP;
+}
diff --git a/src/mainboard/piesia/nm19ne4l/board_info.txt b/src/mainboard/piesia/nm19ne4l/board_info.txt
new file mode 100644
index 0000000000..ce96d4728d
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/board_info.txt
@@ -0,0 +1,7 @@
+Vendor name: Piesia
+Board name: NM19NE4L
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/piesia/nm19ne4l/cmos.layout b/src/mainboard/piesia/nm19ne4l/cmos.layout
new file mode 100644
index 0000000000..2b8e1a223c
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/cmos.layout
@@ -0,0 +1,44 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+# coreboot config options: southbridge
+408	1	e	1	nmi
+409	2	e	7	power_on_after_fail
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/piesia/nm19ne4l/data.vbt b/src/mainboard/piesia/nm19ne4l/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..26854eb6ada14dc35d65569dfc091ae0b9af2155
GIT binary patch
diff --git a/src/mainboard/piesia/nm19ne4l/devicetree.cb b/src/mainboard/piesia/nm19ne4l/devicetree.cb
new file mode 100644
index 0000000000..ec56b34e0f
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/devicetree.cb
@@ -0,0 +1,92 @@
+chip soc/intel/baytrail
+
+	register "usb2_comp_bg" = "0x4700"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x3"
+	register "sata_ahci" = "0x1"
+
+	# Do not route USB ports to XHCI
+	register "usb_route_to_xhci" = "0"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	register "vnn_ps2_enable" = "1"
+	register "vcc_ps2_enable" = "1"
+
+	device cpu_cluster 0 on end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 10.0 off end # MMC
+		device pci 11.0 off end # SDIO
+		device pci 12.0 off end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 off end # LPE
+		device pci 17.0 off end # MMC45
+		device pci 18.0 off end # SIO_DMA1
+		device pci 18.1 off end # I2C1
+		device pci 18.2 off end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 on  end # HDA, was off
+		device pci 1c.0 on  end # PCI-e #1 (LAN1)
+		device pci 1c.1 on  end # PCI-e #2 (LAN2)
+		device pci 1c.2 on  end # PCI-e #3 (LAN3)
+		device pci 1c.3 on  end # PCI-e #4 (LAN4)
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 off end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+
+		device pci 1f.0 on      # LPC
+			chip superio/ite/it8613e
+				device pnp 2e.0 off end	# Floppy
+				device pnp 2e.1 on	# COM1
+					io  0x60 = 0x03f8
+					irq 0x70 = 4
+				end
+				device pnp 2e.2 off end	# COM2
+				device pnp 2e.3 off end	# Parallel port
+				device pnp 2e.4 on	# Environment Controller
+					# io  0x60 = 0x0a30
+					io  0x60 = 0x0a30
+					irq 0x70 = 9
+					io  0x62 = 0x0a20
+				end
+				device pnp 2e.5 off end	# Keyboard
+				device pnp 2e.6 off end	# Mouse
+				device pnp 2e.7 off end	# GPIO
+				device pnp 2e.a off end	# CIR
+			end
+		end
+
+		device pci 1f.3 on  end # SMBus
+	end
+end
diff --git a/src/mainboard/piesia/nm19ne4l/dsdt.asl b/src/mainboard/piesia/nm19ne4l/dsdt.asl
new file mode 100644
index 0000000000..3e021bf1cb
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/baytrail/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/baytrail/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/baytrail/acpi/southcluster.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/piesia/nm19ne4l/early_init.c b/src/mainboard/piesia/nm19ne4l/early_init.c
new file mode 100644
index 0000000000..9921a68274
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/early_init.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8613e/it8613e.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, 0x01)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable serial port */
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/piesia/nm19ne4l/gpio.c b/src/mainboard/piesia/nm19ne4l/gpio.c
new file mode 100644
index 0000000000..391b1812e2
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/gpio.c
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_FUNC2,			/* DDI0_HPD */
+	GPIO_FUNC2,			/* DDI0_DDCDATA */
+	GPIO_FUNC2,			/* DDI0_DDCCLK */
+	GPIO_NC,			/* GPIO_S0_NC[03] */
+	GPIO_NC,			/* GPIO_S0_NC[04] */
+	GPIO_NC,			/* GPIO_S0_NC[05] */
+	GPIO_INPUT,			/* GPIO_S0_NC[06] */
+	GPIO_INPUT,			/* GPIO_S0_NC[07] */
+	GPIO_INPUT,			/* GPIO_S0_NC[08] */
+	GPIO_INPUT,			/* GPIO_S0_NC[09] */
+	GPIO_INPUT,			/* GPIO_S0_NC[10] */
+	GPIO_INPUT,			/* GPIO_S0_NC[11] */
+	GPIO_INPUT,			/* GPIO_S0_NC[12] */
+	GPIO_INPUT,			/* GPIO_S0_NC[13] */
+	GPIO_INPUT,			/* GPIO_S0_NC[14] */
+	GPIO_INPUT,			/* GPIO_S0_NC[15] */
+	GPIO_INPUT,			/* GPIO_S0_NC[16] */
+	GPIO_INPUT,			/* GPIO_S0_NC[17] */
+	GPIO_INPUT,			/* GPIO_S0_NC[18] */
+	GPIO_INPUT,			/* GPIO_S0_NC[19] */
+	GPIO_INPUT,			/* GPIO_S0_NC[20] */
+	GPIO_INPUT,			/* GPIO_S0_NC[21] */
+	GPIO_INPUT,			/* GPIO_S0_NC[22] */
+	GPIO_INPUT,			/* GPIO_S0_NC[23] */
+	GPIO_INPUT,			/* GPIO_S0_NC[24] */
+	GPIO_INPUT,			/* GPIO_S0_NC[25] */
+	GPIO_INPUT,			/* GPIO_S0_NC[26] */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_INPUT,			/* GPIO_S0_SC[000] */
+	GPIO_FUNC2,			/* SATA_DEVSLP[0] */
+	GPIO_FUNC1,			/* SATA_LED# */
+	GPIO_FUNC1,			/* PCIE_CLKREQ[0]# */
+	GPIO_FUNC1,			/* PCIE_CLKREQ[1]# */
+	GPIO_FUNC1,			/* PCIE_CLKREQ[2]# */
+	GPIO_FUNC1,			/* PCIE_CLKREQ[3]# */
+	GPIO_INPUT,			/* GPIO_S0_SC[007] */
+	GPIO_INPUT,			/* GPIO_S0_SC[008] */
+	GPIO_INPUT,			/* GPIO_S0_SC[009] */
+	GPIO_INPUT,			/* GPIO_S0_SC[010] */
+	GPIO_INPUT,			/* GPIO_S0_SC[011] */
+	GPIO_INPUT,			/* GPIO_S0_SC[012] */
+	GPIO_INPUT,			/* GPIO_S0_SC[013] */
+	GPIO_INPUT,			/* GPIO_S0_SC[014] */
+	GPIO_INPUT,			/* GPIO_S0_SC[015] */
+	GPIO_INPUT,			/* GPIO_S0_SC[016] */
+	GPIO_INPUT,			/* GPIO_S0_SC[017] */
+	GPIO_INPUT,			/* GPIO_S0_SC[018] */
+	GPIO_INPUT,			/* GPIO_S0_SC[019] */
+	GPIO_INPUT,			/* GPIO_S0_SC[020] */
+	GPIO_INPUT,			/* GPIO_S0_SC[021] */
+	GPIO_INPUT,			/* GPIO_S0_SC[022] */
+	GPIO_INPUT,			/* GPIO_S0_SC[023] */
+	GPIO_INPUT,			/* GPIO_S0_SC[024] */
+	GPIO_INPUT,			/* GPIO_S0_SC[025] */
+	GPIO_INPUT,			/* GPIO_S0_SC[026] */
+	GPIO_INPUT,			/* GPIO_S0_SC[027] */
+	GPIO_INPUT,			/* GPIO_S0_SC[028] */
+	GPIO_INPUT,			/* GPIO_S0_SC[029] */
+	GPIO_INPUT,			/* GPIO_S0_SC[030] */
+	GPIO_INPUT,			/* GPIO_S0_SC[031] */
+	GPIO_INPUT,			/* GPIO_S0_SC[032] */
+	GPIO_INPUT,			/* GPIO_S0_SC[033] */
+	GPIO_INPUT,			/* GPIO_S0_SC[034] */
+	GPIO_INPUT,			/* GPIO_S0_SC[035] */
+	GPIO_INPUT,			/* GPIO_S0_SC[036] */
+	GPIO_INPUT,			/* GPIO_S0_SC[037] */
+	GPIO_INPUT,			/* GPIO_S0_SC[038] */
+	GPIO_INPUT,			/* GPIO_S0_SC[039] */
+	GPIO_INPUT,			/* GPIO_S0_SC[040] */
+	GPIO_INPUT,			/* GPIO_S0_SC[041] */
+	GPIO_FUNC1,			/* ILB_LPC_AD[0] */
+	GPIO_FUNC1,			/* ILB_LPC_AD[1] */
+	GPIO_FUNC1,			/* ILB_LPC_AD[2] */
+	GPIO_FUNC1,			/* ILB_LPC_AD[3] */
+	GPIO_FUNC1,			/* ILB_LPC_FRAME# */
+	GPIO_FUNC1,			/* ILB_LPC_CLK[0] */
+	GPIO_FUNC1,			/* ILB_LPC_CLK[1] */
+	GPIO_FUNC1,			/* ILB_LPC_CLKRUN# */
+	GPIO_FUNC1,			/* ILB_LPC_SERIRQ */
+	GPIO_FUNC1,			/* PCU_SMB_DATA */
+	GPIO_FUNC1,			/* PCU_SMB_CLK */
+	GPIO_FUNC1,			/* PCU_SMB_ALERT# */
+	GPIO_FUNC1,			/* ILB_8254_SPKR */
+	GPIO_INPUT,			/* GPIO_S0_SC[055] */
+	GPIO_INPUT,			/* GPIO_S0_SC[056] */
+	GPIO_INPUT,			/* GPIO_S0_SC[057] */
+	GPIO_INPUT,			/* GPIO_S0_SC[058] */
+	GPIO_INPUT,			/* GPIO_S0_SC[059] */
+	GPIO_INPUT,			/* GPIO_S0_SC[060] */
+	GPIO_INPUT,			/* GPIO_S0_SC[061] */
+	GPIO_INPUT,			/* GPIO_S0_SC[062] */
+	GPIO_INPUT,			/* GPIO_S0_SC[063] */
+	GPIO_INPUT,			/* GPIO_S0_SC[064] */
+	GPIO_INPUT,			/* GPIO_S0_SC[065] */
+	GPIO_INPUT,			/* GPIO_S0_SC[066] */
+	GPIO_INPUT,			/* GPIO_S0_SC[067] */
+	GPIO_INPUT,			/* GPIO_S0_SC[068] */
+	GPIO_INPUT,			/* GPIO_S0_SC[069] */
+	GPIO_INPUT,			/* GPIO_S0_SC[070] */
+	GPIO_INPUT,			/* GPIO_S0_SC[071] */
+	GPIO_INPUT,			/* GPIO_S0_SC[072] */
+	GPIO_INPUT,			/* GPIO_S0_SC[073] */
+	GPIO_INPUT,			/* GPIO_S0_SC[074] */
+	GPIO_INPUT,			/* GPIO_S0_SC[075] */
+	GPIO_INPUT,			/* GPIO_S0_SC[076] */
+	GPIO_INPUT,			/* GPIO_S0_SC[077] */
+	GPIO_INPUT,			/* GPIO_S0_SC[078] */
+	GPIO_INPUT,			/* GPIO_S0_SC[079] */
+	GPIO_INPUT,			/* GPIO_S0_SC[080] */
+	GPIO_INPUT,			/* GPIO_S0_SC[081] */
+	GPIO_INPUT,			/* GPIO_S0_SC[082] */
+	GPIO_INPUT,			/* GPIO_S0_SC[083] */
+	GPIO_INPUT,			/* GPIO_S0_SC[084] */
+	GPIO_INPUT,			/* GPIO_S0_SC[085] */
+	GPIO_INPUT,			/* GPIO_S0_SC[086] */
+	GPIO_INPUT,			/* GPIO_S0_SC[087] */
+	GPIO_INPUT,			/* GPIO_S0_SC[088] */
+	GPIO_INPUT,			/* GPIO_S0_SC[089] */
+	GPIO_INPUT,			/* GPIO_S0_SC[090] */
+	GPIO_INPUT,			/* GPIO_S0_SC[091] */
+	GPIO_INPUT,			/* GPIO_S0_SC[092] */
+	GPIO_INPUT,			/* GPIO_S0_SC[093] */
+	GPIO_INPUT,			/* GPIO_S0_SC[094] */
+	GPIO_INPUT,			/* GPIO_S0_SC[095] */
+	GPIO_INPUT,			/* GPIO_S0_SC[096] */
+	GPIO_INPUT,			/* GPIO_S0_SC[097] */
+	GPIO_INPUT,			/* GPIO_S0_SC[098] */
+	GPIO_INPUT,			/* GPIO_S0_SC[099] */
+	GPIO_INPUT,			/* GPIO_S0_SC[100] */
+	GPIO_INPUT,			/* GPIO_S0_SC[101] */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_INPUT,			/* GPIO_S5[00] */
+	GPIO_FUNC6,			/* PMC_WAKE_PCIE[1]# */
+	GPIO_FUNC6,			/* PMC_WAKE_PCIE[2]# */
+	GPIO_FUNC6,			/* PMC_WAKE_PCIE[3]# */
+	GPIO_INPUT,			/* GPIO_S5[04] */
+	GPIO_INPUT,			/* GPIO_S5[05] */
+	GPIO_INPUT,			/* GPIO_S5[06] */
+	GPIO_INPUT,			/* GPIO_S5[07] */
+	GPIO_INPUT,			/* GPIO_S5[08] */
+	GPIO_INPUT,			/* GPIO_S5[09] */
+	GPIO_INPUT,			/* GPIO_S5[10] */
+	GPIO_INPUT,			/* GPIO_S5[11] */
+	GPIO_INPUT,			/* GPIO_S5[12] */
+	GPIO_INPUT,			/* GPIO_S5[13] */
+	GPIO_INPUT,			/* GPIO_S5[14] */
+	GPIO_FUNC0,			/* PMC_WAKE_PCIE[0]# */
+	GPIO_FUNC(0, PULL_UP, 20K),	/* PMC_PWRBTN# */
+	GPIO_INPUT,			/* GPIO_S5[17] */
+	GPIO_INPUT,			/* GPIO_S5[18] */
+	GPIO_INPUT,			/* GPIO_S5[19] */
+	GPIO_INPUT,			/* GPIO_S5[20] */
+	GPIO_INPUT,			/* GPIO_S5[21] */
+	GPIO_INPUT,			/* GPIO_S5[22] */
+	GPIO_INPUT,			/* GPIO_S5[23] */
+	GPIO_INPUT,			/* GPIO_S5[24] */
+	GPIO_INPUT,			/* GPIO_S5[25] */
+	GPIO_INPUT,			/* GPIO_S5[26] */
+	GPIO_INPUT,			/* GPIO_S5[27] */
+	GPIO_INPUT,			/* GPIO_S5[28] */
+	GPIO_INPUT,			/* GPIO_S5[29] */
+	GPIO_INPUT,			/* GPIO_S5[30] */
+	GPIO_INPUT,			/* GPIO_S5[31] */
+	GPIO_INPUT,			/* GPIO_S5[32] */
+	GPIO_INPUT,			/* GPIO_S5[33] */
+	GPIO_INPUT,			/* GPIO_S5[34] */
+	GPIO_INPUT,			/* GPIO_S5[35] */
+	GPIO_INPUT,			/* GPIO_S5[36] */
+	GPIO_INPUT,			/* GPIO_S5[37] */
+	GPIO_INPUT,			/* GPIO_S5[38] */
+	GPIO_INPUT,			/* GPIO_S5[39] */
+	GPIO_INPUT,			/* GPIO_S5[40] */
+	GPIO_INPUT,			/* GPIO_S5[41] */
+	GPIO_INPUT,			/* GPIO_S5[42] */
+	GPIO_INPUT,			/* GPIO_S5[43] */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config *mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}
diff --git a/src/mainboard/piesia/nm19ne4l/irqroute.c b/src/mainboard/piesia/nm19ne4l/irqroute.c
new file mode 100644
index 0000000000..6fa036672e
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/irqroute.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/piesia/nm19ne4l/irqroute.h b/src/mainboard/piesia/nm19ne4l/irqroute.h
new file mode 100644
index 0000000000..946062270d
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/irqroute.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,  A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+	PIRQ_PIC(A, DISABLE), \
+	PIRQ_PIC(B, DISABLE), \
+	PIRQ_PIC(C, DISABLE), \
+	PIRQ_PIC(D, DISABLE), \
+	PIRQ_PIC(E, DISABLE), \
+	PIRQ_PIC(F, DISABLE), \
+	PIRQ_PIC(G, DISABLE), \
+	PIRQ_PIC(H, DISABLE)
diff --git a/src/mainboard/piesia/nm19ne4l/mainboard.c b/src/mainboard/piesia/nm19ne4l/mainboard.c
new file mode 100644
index 0000000000..100cfa514e
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/mainboard.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	/* Install custom int15 handler for VGA OPROM */
+	if (CONFIG(VGA_ROM_RUN))
+		install_baytrail_vga_int15_handler();
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/piesia/nm19ne4l/romstage.c b/src/mainboard/piesia/nm19ne4l/romstage.c
new file mode 100644
index 0000000000..ec18cfc05b
--- /dev/null
+++ b/src/mainboard/piesia/nm19ne4l/romstage.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
+
+void mainboard_fill_mrc_params(struct mrc_params *mp)
+{
+	mp->mainboard.dram_type = DRAM_DDR3L;
+	mp->mainboard.dram_info_location = DRAM_INFO_SPD_SMBUS;
+	mp->mainboard.dram_is_slotted = 1;
+	mp->mainboard.spd_addrs[0] = 0x50; /* Board only has one slot */
+}
diff --git a/src/soc/intel/baytrail/int15.c b/src/soc/intel/baytrail/int15.c
index 62abbc11a6..0cde366a6b 100644
--- a/src/soc/intel/baytrail/int15.c
+++ b/src/soc/intel/baytrail/int15.c
@@ -38,7 +38,8 @@ static int int15_handler(void)
 		 *  bit 7 = LFP2
 		 */
 		X86_AX = 0x005f;
-		X86_CX = 0x0008;
+		// X86_CX = 0x0008; // Default, for eDP
+		X86_CX = 0x0004; // Bit 2 set, for HDMI
 		res = 1;
 		break;
 	case 0x5f51:
